Sure there's a ton of compute chips, gobs of HBM... but honestly the super interesting weird challenge here, besides making this monster boot, is connecting all the chips.
Will CPU & GPU chiplets talk with each other? Or will all communication travel through glue chips like the IO Die? Where does the hbm attach? Is there ram too? On RDNA3, AMD has 6 small Memory Channel Die (and a huge Graphic Compute Die in the center)... will we see similar with HBM be attached to individual GCD?
I'm going to guess that the 6nm chiplets are analogous to the EPYC IO die, and have the IO, memory controllers, and last level cache. The compute dies are stacked on the IO dies, which are stacked on an interposer. The interposer connects the IO dies to each other and to the HBM. The HBM is not stacked on the chiplets because I don't think any current HBM supports that and AMD considers it a future technology: https://www.techpowerup.com/305060/amd-envisions-stacked-dra...
This is a fun theory! I like the view of the IO dies connecting to each other across interposer. That interposer is going to be moving a lot of traffic!
HBM requires a pretty expensive and dense silicon interposer, which should be sufficient to connect the IO dies. They're probably just using an infinity fabric network between the dies anyway so it's pretty high level.
Given that AMD has been making combined cpu+gpus for over a decade I think it's safe to assume that the cpu(s) and gpu(s) will have an efficient communication path with shared access to memory.
> According to AMD, MI300 is comprised of 9 5nm chiplets, sitting on top of 4 6nm chiplets. The 5nm chiplets are undoubtedly the compute logic chipets – i.e. the CPU and GPU chiplets – though a precise breakdown of what’s what is not available. A reasonable guess at this point would be 3 CPU chiplets (8 Zen 4 cores each) paired with possibly 6 GPU chiplets; though there's still some cache chiplets unaccounted for. Meanwhile, taking AMD’s “on top of” statement literally, the 6nm chiplets would then be the base dies all of this sits on top of. Based on AMD’s renders, it looks like there’s 8 HBM3 memory stacks in play, which implies around 5TB/second of memory bandwidth, if not more.
I cant get this to add up when I look at the photo of the chip. Maybe this is the lower layer we have photographed? The photo is a central cluster of 4 huge chiplets, then and 2+2 big+small chiplets next to each.
At first I was trying to imagine this as the top layer, the 9 5nm chiplets, and just couldn't square it.
Maybe the 2+2 are all cache/hbm, and this is the 4 6nm chiplets we're seeing? I wonder if that means the 9 compute chiplets are burried in the stack, but the words "on top" keep making me think otherwise. Or perhaps this photo isn't a complete chip, is missing the top dies?
I'm still more excited to know about how this all connects than anything else. There's such a huge amount of switching required to connect this all. This feels like such a radical change for Infinity Fabric, such a huge step function.
Will CPU & GPU chiplets talk with each other? Or will all communication travel through glue chips like the IO Die? Where does the hbm attach? Is there ram too? On RDNA3, AMD has 6 small Memory Channel Die (and a huge Graphic Compute Die in the center)... will we see similar with HBM be attached to individual GCD?